Minimizing Bitline Coupling Noise in DRAM with Capacitor-Equiplanar-to-Bitline (CEB) Cell Structure
نویسندگان
چکیده
A new scheme of stack DRAM referred to as Capacitor-Equiplanar-to-Bitline (CEB) is proposed for minimizing bitline coupling noises. The cell capacitors are fabricated in between bit-lines, so that the bit-line coupling is blocked by the node capacitor and shielded by the plate. 3D simulation shows that the bit-line coupling noise is almost eliminated (<1% of total bit-line capacitance) in CEB scheme. The SPICE simulation shows ~3ns faster bit-line signal sensing in 0.25um 64Mb CMOS DRAM. The CEB scheme also leads to smaller topology and simpler fabrication process.
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